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Dual-Diameter Variation –Immune CNFET-based 7T SRAM Cell
Aminul Islam, Mohd. Hasan
Pages - 1 - 14     |    Revised - 31-01-2011     |    Published - 08-02-2011
Volume - 1   Issue - 1    |    Publication Date - July / August 2011  Table of Contents
Namoelectronics, Nanotechnology, Nanotubes
This paper proposes a variation – tolerant dual-diameter CNFET-based 7T (seven transistor) SRAM (static random access memory) cell. The use of appropriate DCNT (diameter of CNFET) and hence Vt of CNFETs is a critical piece of our design strategy. In this work, dual-Vt and dual-diameter CNFETs have been used using suitable chiral vectors for appropriate transistors. It also investigates the impact of process, voltage and temperature variations on its design metrics and compares the results with its counterpart − CMOS-based 7T SRAM cell and standard 6T SRAM cell (only few parameters). The proposed SRAM cell offers 1.35× and 1.25× improvement in standby power on an average @ VDD = 1 V and 0.9 V respectively, 30% improvement in SNM (Static Noise Margin) over CMOS-based 7T cell. Proposed design outperforms 6T in terms of 71.4% improvement in RSNM and shows same read stability as its CMOS counterpart, It shows its robustness by offering 1.4× less spread in TRA (read access time) at 1 V and 1.2× less spread in TRA at 0.9 V than that of its CMOS counterpart at the expense of 1.6× read delay. The proposed bitcell also exhibits higher performance while writing (takes 1.3× and 1.2× less TWA (write access time) @ VDD = 1 V and VDD= 0.9 V respectively). It also proves its robustness against process variations by featuring tighter spread in TWA variability (1.4× and 1.2× @ VDD= 1 V and 0.9 V respectively).
CITED BY (2)  
1 Srivastava, p., & islam, a. (2015). cnfet-based design of resilient mcml xor/xnor circuit at 16-nm technology node. indian journal of engineering & materials sciences, 22, 261-267.
2 Islam, a. (2014). power and variability aware design of circuits and systems.
1 Google Scholar 
2 CiteSeerX 
3 refSeek 
4 Scribd 
5 SlideShare 
6 PdfSR 
A. Javey, J. Guo, D. B. Farmer, Q. Wang, D. Wang, R. G. Gordon, M. Lundstrom, and H. Dai. “Carbon nanotube field-effect transistors with integrated ohmic contacts and high-k gate dielectrics”. Nano Lett., 4(3):447–450, 2004.
A. Javey, J. Guo, D. B. Farmer, Q. Wang, E. Yenilmez, R. G. Gordon, M. Lundstrom, and H. Dai. “Self-aligned ballistic molecular transistors and electrically parallel nanotube arrays”. Nano Lett., 4(7):1319–1322, 2004.
A. Lin, et al. “Threshold voltage and on-off ratio tuning for multiple-tube carbon nanotube FETs”. IEEE Trans. Nanotechnol., 8(1):4-9, 2009.
A. Naeemi, R. Sarvari, and J. D. Meindl. “Performance comparison between carbon nanotube and copper interconnects for gigascale integration (GSI)”. IEEE Electron Device Lett., 26(2): 84–86, 2005.
A. Raychowdhury and K. Roy. “A circuit model for carbon nanotube interconnects: comparative study with Cu interconnects for scaled technologies”. In Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD ’04), 237–240, 2004.
A. Raychowdhury and K. Roy. “Modeling of metallic carbonnanotube interconnects for circuit simulations and a comparison with Cu interconnects for scaled technologies”. IEEE Trans. Comput.-Aided Des. Integr. Syst., 25(1):58–65, 2006.
B. H. Calhoun, and Anantha P. Chandrakasan. “Static Noise Margin Variation for Subthreshold SRAM in 65-nm CMOS”. IEEE J. Solid State Circuits, 42(7), 2006.
Berkeley Predictive Technology Model, UC Berkeley Device Group. [Online]. Available: http://www-device.eecs.berkeley.edu/~ptm/.
D. Akinwande, et al. “Monolithic integration of CMOS VLSI and carbon nanotubes for hybrid nanotechnology application”. IEEE Trans. Nanotechnol., 7(5):636-639, 2008.
D. Burnett, K. Erington, C. Subramanian, and K. Baker. “Implications of fundamental threshold voltage variations for high-density SRAM and logic circuits”. In Proceedings of the Symp. VLSI Tech., 15–16, 1994.
D. Mann, A. Javey, J. Kong, Q. Wang, and H. Dai. “Ballistic transport in metallic nanotubes with reliable Pd ohmic contacts”. Nano Lett., 3(11):1541–1544, 2003.
G. Zhang, et al. “Selective etching of metallic carbon nanotubes by gas-phase reaction”. Science, 314(5801):974-977, 2006.
H. Dai. “Carbon nanotubes: synthesis, integration, and properties”. Acc. Chem. Res. 35(12):1035-1044, 2002.
H. J. Li, W. G. Lu, J. J. Li, X. D. Bai, and C. Z. Gu, “Multichannel ballistic transport in multiwall carbon nanotubes,” Physical Review Letters, 95(8), Article ID 086601, 4 pages, 2005.
H. Qin, Y. Cao, D. Markovic, A. Vladimirescu, and J. Rabaey. “SRAM leakage suppression by minimizing standby supply voltage”. In Proceedings of the Int. Symp. Quality Electron. Des., 55-60, 2004.
I. Amlani, J. Lewis, K. Lee, R. Zhang, J. Deng, and H.-S. P. Wong. “First demonstration of AC gain from a single-walled carbon nanotube common-source amplifier”. In Proceedings of the Int. Electron Devices Meet., 1-4, 2006.
J. Deng, H.-S. P. Wong. “A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application - Part I: Model of the Intrinsic Channel Region”. IEEE Trans. Electron Devices, 54(12):3186-3194, 2007
J. Deng, H.-S. P. Wong. “A Compact SPICE Model for Carbon-Nanotube Field-Effect Transistors Including Nonidealities and Its Application - Part II: Full Device Model and Circuit Performance Benchmarking”. IEEE Trans. Electron Devices, 54(12):3195-3205, 2007.
J. Zhang, et at.. “Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement”. In Proceedins of the DAC 2010, Anatheim, California, USA, 889-892, 2010.
J. Zhang, N. Patil and S. Mitra. “Probabilistic analysis and design of metallic-carbonnanotube- tolerant digital logic circuits”. IEEE Trans. Comput.-Aided Des. Integr. Syst, 28(9):1307-1320, 2009.
K. Roy, S. Mukhopadhyay, and H. Mahmoodi-Meimand. “Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits”. In Proceedings of the IEEE, 91(2):305–327, 2003.
L. Ding, et al. “Selective growth of well-aligned semiconducting single-walled carbon nanotubes”. Nano Letters, 9(2):800-805, 2009.
M. Engel, et al. “Thin film nanotube transistors based on self-assembled, aligned, semiconducting carbon nanotube arrays”. ACS Nano, 2(12):2445-2452, 2008.
M. LeMieux, et al. “Self-sorted, aligned nanotube networks for thin-film transistors”. Science, 321(5885):101-104, 2008.
N. Hamada, S.-I. Sawada, and A. Oshiyama. “New one-dimensional conductors: graphite microtubules.” Phys. Rev. Lett., 68(10):1579–1581, 1992.
N. Patil, Albert Lin, Jie Zhang, Hai Wei, Kyle Anderson H. -S. Philip Wong and Subhasish Mitra. “Scalable carbon nanotube computational and storage circuits immune to metallic and mis-positioned carbon nanotubes”. IEEE Trans. Nanotechnol., 99, 2010.
N. Patil, et al.. “Design methods for misaligned and mis-positioned carbon-nanotube-immune circuits”. IEEE Trans. Comput.-Aided Des. Integr. Syst. 27(10):1725-1736, 2008.
N. Srivastava and K. Banerjee. “A comparative scaling analysis of metallic and carbon nanotube interconnections for nanometer scale VLSI technologies”. In Proceedings of the 21st International VLSI Multilevel Interconnection Conference (VMIC ’04). 393–398, 2004.
orkar, S., et al. “Statistical circuit design with carbon nanotubes”. U.S. Patent Application 20070155065, 2005.
P. G. Collins, M. S. Arnold and P. Avouris. “Engineering carbon nanotubes and nanotube circuits using electrical breakdown”. Science, 292:706-709, 2001.
P. McEuen, M. Fuhrer, and H. Park, “Single-walled carbon nanotube electronics”. IEEE Trans. Nanotechnol., 1(1):pp. 78–85, 2002.
R. Aly, M. Faisal, and A. Bayoumi. “Novel 7T SRAM cell for low power cache design”. In Proceedings of the IEEE SOC Conf., 171–174, 2005.
S. Rusu, S. Tam, H. Muljono, D. Ayers, J. Chang, B. Cherkauer, J. Stinson, J. Benoit, R. Varada, J. Leung, et al. “A 65-nm Dual-Core Multithreaded Xeon Processor With 16-MB L3 Cache”. IEEE J. Solid-State Circuits, 42(1): 17-25, 2007.
Stanford University CNFETModelWeb site. (2008). [Online]. Available: http://nano.stanford.edu/model.php?id=23
Y. Cui, Z. Zhong, D. Wang, W. U. Wang, and C. M. Lieber. “High performance silicon nanowire field effect transistors”. Nano Lett., 3(2):149–152, 2003.
Y. Li, et al. “Preferential growth of semiconducting single-walled carbon nanotubes by a plasma enhanced CVD method”. Nano Letters, 4(2):317-321, 2004.
Z. Yao, C. L. Kane, and C. Dekker. “High-field electrical transport in single-wall carbon nanotubes”. Phys. Rev. Lett., 84(13):2941– 2944, 2000.
Associate Professor Aminul Islam
Birla Institute of Technology (deemed university) - India
Professor Mohd. Hasan
Aligarh Muslim University - India

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