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Reliability Improvement in Logic Circuit Stochastic Computation
Jeremy Michael Lakes, Samuel C. Lee
Pages - 22 - 30     |    Revised - 01-07-2011     |    Published - 05-08-2011
Volume - 2   Issue - 2    |    Publication Date - July / August 2011  Table of Contents
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KEYWORDS
Digital Design, Fault Tolerance, Reliability, Stochastic Model, Noisy Signals
ABSTRACT
Defects and faults arise from physical imperfections and noise susceptibility of the analog circuit components used to create digital circuits resulting in computational errors. A probabilistic computational model is needed to quantify and analyze the effect of noisy signals on computational accuracy in digital circuits. This model computes the reliability of digital circuits meaning that the inputs and outputs and their implemented logic function need to be calculated probabilistically. The purpose of this paper is to present a new architecture for designing noise-tolerant digital circuits. The approach we propose is to use a class of single-input, single-output circuits called Reliability Enhancement Network Chain (RENC). A RENC is a concatenation of n simple logic circuits called Reliability Enhancement Network (REN). Each REN can increase the reliability of a digital circuit to a higher level. Reliability of the circuit can approach any desirable level when a RENC composed of a sufficient number of RENs is employed. Moreover, the proposed approach is applicable to the design of any logic circuit implemented with any logic technology.
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D. Bhaduri and S. K. Shukla. "Reliability evaluation of von Neumann multiplexing based defect-tolerant majority circuits" Nanotechnology, 2004. 4th IEEE Conference on , vol., no., pp. 599-601, 16-19 Aug. 2004.
G. Norman, D. Parker, M. Kwiatkowska and S. Shukla.”Evaluating reliability of defect tolerant architecture for nanotechnology using probabilistic model checking” in Proc. IEEE VLSI Design Conference (IEEE Press, 2004), to appear.
J. von Neumann,”Probabilistic logics and the synthesis of reliable organisms from unreliable components,” in Automata Studies, C.E. Shannon and J. McCarthy, Eds. Princeton, NJ:Princeton University Press, 1956, pp. 43-98.
Jie Han and Pieter Jonker.“A System Architecture Solution for Unreliable Nanoelectronic Devices” IEEE Trans. on Nanotechnology, vol. 1, no. 4, pp. 201-208, December 2002.
K. Nikolic, A. Sadek and M. Forshaw.”Architectures for Reliable Computing with Unreliable Nanpdevices” in Proc. IEEE-NANO ’01 (IEEE 2001), pp. 254-259.
N. Pippenger. “Invariance of complexity measures for networks with unreliable gates” J. ACM, vol 36, pp. 194-197, 1988.
N. Pippenger. “On networks of noisy gates” in Proc. 26thAnnu. Symp. Foundationas of Computer Science, pp. 30-38, 1985.
N. Pippenger. “Reliable computation by formulas in the presence of noise,” IEEE Trans. Inform. Theory, vol. 34, pp. 194-197, 1988.
R. L. Dobrushin and S. I. Ortyukov.“Lower bound on the redundancy of self-correcting arrangements of unreliable functional elements” Prob. Inform. Trans., vol. 13, pp. 59- 65, 1977.
R. L. Dobrushin and S. I. Ortyukov.“Upper bound on the redundancy of self-correcting arrangements of unreliable functional elements” Prob. Inform. Trans., vol. 13, pp. 203- 218, 1977.
S. Ahuja, G. Singh, D. Bhaduri, and S. Shukla.”Fault- and Defect-Tolerant Architectures for Nanocomputing” in Bio-inspired and Nanoscale: Integrated Computing, M. Wilner, Ed. New Jersey: Wiley, 2009, pp. 262-293.
S. C. Lee and L. R. Hook. "Logic and Computer Design in Nanospace" IEEE Transactions on Computers, vol. 57, no. 7, pp. 965-977, 2008.
S. C. Lee and L. R. Hook."Toward the design of a nanocomputer" in Proc. IEEE 2006 Canadian Conference on Electrical and Computer Engineering, May 2006.
S. Yanushkevich, V. Shmerko, and S. Lyshevski.Computer Arithmetics for Nanoelectronics. Boca Raton: CRC Press, 2009.
S. Yanushkevich, V. Shmerko, and S. Lyshevski.Logic Design of NanoICs. Boca Raton: CRC Press, 2005.
T. Rejimon, K. Lingasurbramanian, and S. Bhanja.“Probabilistic Error Modeling for Nano-Domain Logic Circuits” IEEE Trans. On VLSI, vol. 17, no. 1, pp. 55-65, January 2009.
W. Evans and N. Pippenger.“On the maximum tolerable noise for reliable computation by formulas” IEEE Trans. Inform. Theory, vol. 44, pp. 1299-1305, 1998.
W.R. Fahrner, Ed., Nanotechnology and Nanoelectronics: Materials, Devices, Measurement Techniques. Berlin: Springer, 2005, pp. 18-38.
X. Lu and J. Li.”Probabilistic Modeling of Nanoscale XOR Gate” in International Conference on Apperceiving Computing and Intelligence Analysis, 2008, pp. 4-7.
X. Lu, J. Li, G. Yang, and X. Song.”Probabilistic Modeling of Nanoscale Adder” in IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, 2008.
Mr. Jeremy Michael Lakes
University of Oklahoma - United States of America
jlakes@ou.edu
Dr. Samuel C. Lee
University of Oklahoma - United States of America


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