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System Level Power Management for Embedded Rtos: An Object Oriented Approach
Ankur Agarwal, E. B. Fernandez
Pages - 488 - 500     |    Revised - 30-10-2009     |    Published - 30-11-2009
Volume - 3   Issue - 5    |    Publication Date - November 2009  Table of Contents
Tolerance allocation, Optimization techniques, Alternative process selection, Lagrange’s multiplier method, Bottom curve follower approach
Power management systems for embedded devices can be developed in real-time operating system (RTOS) or in applications. If power management policies are applied in operating system (OS), then designers and developers will not have to worry about complex power management algorithms and techniques. They can rather concentrate on application development. The OS contains specific and accurate information about the various tasks being executed. An RTOS further has a comprehensive set of power management application programming interfaces (APIs) for both device drivers and applications within a power management component. Therefore, it is logical to place policies and algorithms in the OS that can place components not being used into lower power states. This can significantly reduce the system energy consumption. We present here an abstract model of a system power manager (PM), device power managers, and application power managers. We present relationship and interactions of these managers with each other using Unified Modeling Language (UML) class diagrams, sequence diagrams and state charts. We recommend that the PM must be implemented at the OS level in any embedded device. We also recommend the interfaces for interactions between PM and the devices power manager, as well as PM and application power manager. Device driver and application developers can easily use this object oriented approach to make the embedded system more power efficient, easy to maintain, and faster to develop.
CITED BY (2)  
1 Prabakaran, R., Arivazhagan, S., & Prabakaran, S. (2012). Power estimation techniques for embedded and VLSI system: A survey.
2 Brihi, A. A. H. Investigation into the dependency between resource utilization, power consumption and performance in Multimedia servers.
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A. Agarwal, S. Rajput, A. S. Pandya, “Power management System for Embedded RTOS: An Object Oriented Approach”, IEEE Canadian Conference on Electrical and Computer Engineering, May 2006, pp. 2305-2309
A. Sagahyroon, M. Karunaratne, “Impact of cache optimization techniques on energy management”, IEEE Canadian Conference on Electrical and Computer Engineering, Volume 4, May 2004, pp. 1831-1833
A. Weissel, F. Bellosa, “Process cruise control: event-driven clock scaling for dynamic power management”, IEEE Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, October 2002.
“Adaptive Power Management for Mobile Hard Drives”, IBM, April 1999, http://www.almaden.ibm.com/almaden/pbwhitepaper.pdf
“Embedded Processor Performance Parameter Data-Sheet”www.intel.com
“Roadmap Architects – The Technology Working Groups” http://public.itrs.net
Bittl JA, Ryan TJ, Keaney JF. “Coronary artery perforation during excimer laser coronary angioplasty”. J Am Coll Cardiol. 1993;2 1: 1158-1165.
Burd T. D., Brodersen R. W., “Energy efficient CMOS microprocessor design” In Proceedings of the 28th Annual Hawaii International Conference on System Sciences. Volume 1: Architecture, IEEE Computer Society Press, 1995, pp. 288-297
C. Grelu, N. Baboux, .A. Bianchi, C. Plossu, “Low switching losses devices architectures for power management applications integrated in a low cost 0.13/spl mu/m CMOS technology”, 35th IEEE Proceedings of Solid-State Device research Conference, September 2005, pp 477-480
C. Le, P. Nathaniel, L. H. Yung, “Joint power management of memory and disk under performance constraints”, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Volume 25, issue 12, December 2006, pp. 2697-2711.
D. Grunwald, P. Levis, C. Morrey III, M. Neufeld, K. Farkas, “Policies for dynamic clock scheduling”, Symposium on Operating Systems Design and Implementation, October 2000, pp 78-86
D. Monticelli, “System approaches to power management”, 17th Annual IEEE Conference and Exposition on Applied Power Electronics, Volume 1, March 2002, pp. 3-7
H.S. Choi, D. Y. Huh, “Power Electronics Specialists Conference 2005”, 36th IEEE Power Electronics Specialists Conference, 2005, pp. 2817-2822
J. Byoun, P. L. Chapman, “Central power management unit as portable power management architecture based on true digital control”, IEEE Workshop on Computers in Power Electronics, August 2004, pp. 69-73
Jenson Douglas E., “Real-time design pattern robust scalable architecture for real time systems”, Boston, Addition-Wesley, 2002.
K. Lahiri, A. Raghunathan, “Power analysis of system-level on-chip communication architectures”, IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES + ISSS), 2004, pp. 236-241.
L. Benini, A. Bogliolo, G. D. Micheli, “A survey of design techniques for system-level dynamic power management”, IEEE Transactions on very large Scale Integration Systems, Volume 8, Issue 3, June 2000, pp. 299-316
L. Benini, R. Hodgson., P. Siegel, “System-level power estimation and optimization”, International Symposium on Low Power Electronics and Design, IEEE Conference, pp. 173-178, August 1998.
L. Benini, S. K. Shuklam, R. K. Gupta, “Tutorial: architectural system level and protocol level techniques for power optimization for networked embedded systems”, 18th International Conference on VLSI Design, January 2005, pp. 18
L.S. Brakmo, D.A. Wallach, M.A. Viredaz, “uSleep: A technique for reducing energy consumption in handheld device”, 2nd IEEE International Conference Proceeding on Mobile Systems Applications, and Services, June 2004.
M. Fukashi, H. Isamu, G. Takayuki, N. Hideyuki, I. Takashi, S. Hiroki, D. Katsumi, A. Kazutami, “A configurable enhanced TTRAM macro for system-level power management unified memory”, IEEE Journal of Solid-State Circuits, Volume 42, Issue 4, April 2007, pp. 852-861.
Martin Timmerman, “RTOS Evaluations”, 2000, http://www.dedicated-systems.com
Q. Qiu, Q. Wu, M. Pedram, “Dynamic power management in mobile multimedia system with guaranteed quality-of-service”, IEEE Design Automation Conference, Vol. 49, pp 834-849. June 2001.
Q. Zhu, Y. Zhou, “Power aware storage cache management”, IEEE Transactions on Computers, Volume 54, issue 5, May 2005, pp. 587-602.
R. M. Passos, C. J. N. Coelho, A. A. F. Loureiro, R. A. F Minim, “Dynamic power management in wireless sensor networks: an application-driven approach”, 2nd Annual IEEE Conference on Wireless on-demand Network Systems and Services, January 2005, pp. 109-118
S. Gurumurthi, A. Sivasubramaniam, M. Kandemir, H. Franke, “Reducing disk power consumption in servers with drpm” IEEE Computer, Volume 36, Issue 12, December 2003, pp. 59-66
S. Vaddagiri, A.K. Santhanam, V. Sukthankar, and M. Iyer, “Power management in linux-based systems,” Linux Journal, March 2004, http://www.linuxjournal.com/article.php?sid=6699.
Sinha A., Chandrakasan A. P., “Energy efficient real-time scheduling [Microprocessors]”, IEEE International Conference of Computer Aided Design, pp. 458-463, November 2001.
T. Simunic, S. P. Boyd, P. Glynn, “Managing power consumption in network on chips”, IEEE Transactions on Very large Scale Systems, Volume 12, Issue 1, January 2004, pp. 96-107
Udani, S., Smith, J., “Power management in mobile computing”, Department of Computer Information Sciences, Technical Report, University of Pennsylvania, February 1998.
Y. H. Lu, L. Benini, G. D. Micheli, “Power aware operating systems for interactive systems”, IEEE Transactions on Very Large Scale Integration Systems, Volume 10, Issue 2, April 2002, pp. 119-134
Y. H. Lu, T. Simuni´c, G. D. Micheli, “Software controlled power management”, IEEE International Workshop on Hardware/Software Codesign, 1999, pp. 157–161.
Y. J. Lu, A. C. W. Wai, L. L. Wei Fan, B. K. Lok, P. Hyunjeong, K. Joungho, “Hybrid analytical modeling method for split power bus in multilayer package”, IEEE Transactions on Electromagnetic Compatibility, Volume 48, Issue 1, February 2006, pp. 82-94.
Y.-H. Lu, E.-Y. Chung, T. ?Simuni´c, L. Benini, G. D. Micheli, “Quantitative comparison of power management algorithms”, IEEE Conference on Design Automation and Test in Europe, March 2000, pp. 20-26
Y.-H. Lu, G. D. Micheli, “Comparing system-level power management policies”, IEEE Design & Test of Computers special issue on Dynamic Power Management of Electronic Systems, pages 10–19, March/April 2001.
Yung-Hsiang Lu and Giovanni De Micheli, “Adaptive hard disk power management on personal computers”, Great Lakes Symposium on VLSI, 1999, pp. 50–53.
Zimmermann, R., and Fichtner, W., “Low power logic styles: CMOS versus pass-transistor logic”, IEEE Journal of Solid State Circuits, Vol. 32, pp. 1079-1089.
Dr. Ankur Agarwal
- United States of America
Professor E. B. Fernandez
Florida Atlantic University - United States of America

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